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| Preliminary EMC326SP16AJ 2Mx16 CellularRAM Document Title 2Mx16 bit CellularRAM Revision History Revision No. 0.0 History Initial Draft Draft Date July 05,2007 Remark Preliminary Emerging Memory & Logic Solutions Inc. 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-717 Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com 1 The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. Preliminary EMC326SP16AJ 2Mx16 CellularRAM 32Mb Async/Page/Burst CellularRAM FEATURES - Sigle device supports asynchrous, page and burst operation - Vcc, VccQ voltages: 1.7V~1.95V VCC 1.7V~1.95V VCCQ - Random access time: 70ns - Burst mode READ and WRITE access: 4, 8, 16, or 32 words, or continuous burst Burst wrap or sequential Max clock rate: 104 MHz (tCLK = 9.62ns) , 133MHz(tCLK = 7.5ns) Burst initial latency: 38.5ns (4 clocks) @ 104 MHz , 37.5ns(5 clocks) @ 133 MHz tACLK: 7ns @ 104 MHz , 5.5ns @ 133 MHz - Page mode READ access: Sixteen-word page size Interpage READ access : 70ns Intrapage READ access : 20ns - Low power consumption: Asynchronous READ: <25mA Intra page READ: <15mA Initial access, burst READ: (37.5ns [5 clocks] @ 133 MHz) <40mA Continuous burst READ: <35mA Deep power down: < 10uA(max.) - Low-power features On-chip temperature compensated self refresh (TCSR) Partial array refresh (PAR) Deep Power-down(DPD) mode OPTIONS - Configuration: 32Mb (2 megabit x 16) - Vcc core / VccQ I/O voltage supply: 1.8V - Timing: 70ns access - Frequency: 83 MHz, 104 MHz, 133 MHz - Standby current at 85C Low Low Power : 100A(max) Low Power : 120A(max) Standard : 140A(max) - Operating temperature range: Wireless -30C to +85C 2 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Table of Contents Features ................................................................................................................................................................................. Options ............................................................................................................................................................................... General Description ................................................................................................................................................................ Functional Description ............................................................................................................................................................ Power-Up Initialization ....................................................................................................................................................... Bus Operating Modes ............................................................................................................................................................. Asynchronous Mode .......................................................................................................................................................... Page Mode READ Operation ............................................................................................................................................ Burst Mode Operation ........................................................................................................................................................ Mixed-Mode Operation ....................................................................................................................................................... WAIT Operation ................................................................................................................................................................. LB# / UB# Operation........................................................................................................................................................... Low-Power Operation......... .................................................................................................................................................... Standby Mode Operation ................................................................................................................................................... Temperature Compensated Refresh................................................................................................................................... Partial Array Refresh .......................................................................................................................................................... Deep Power-Down Operation............................................................................................................................................. Registers................................................................................................................................................................................. Access Using CRE ............................................................................................................................................................. Software Access ................................................................................................................................................................ Bus Configuration Register................................................................................................................................................. Burst Length (BCR[2:0]) Default = Continuous Burst ..................................................................................................... Burst Wrap (BCR[3]) Default = No Wrap ........................................................................................................................ Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength ........................................................................... WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid / Invalid................................... WAIT Polarity (BCR[10]) Default = WAIT Active HIGH................................................................................................... Latency Counter (BCR[13:11]) Default = Three Clock Latency .................................................................................... Initial Access Latency (BCR[14]) Default = Variable....................................................................................................... Operating Mode (BCR[15]) Default = Asynchronous Operation..................................................................................... Refresh Configuration Register........................................................................................................................................... Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh ..................................................................................... Deep Power-Down (RCR[4]) Default = DPD Disabled ................................................................................................... Page Mode Operation (RCR[7]) Default = Disabled ...................................................................................................... Device Identification Register.............................................................................................................................................. Electrical Characteristics......................................................................................................................................................... Timing Requirements.............................................................................................................................................................. Timing Diagrams..................................................................................................................................................................... 2 2 6 9 9 10 10 11 12 15 15 15 16 16 16 16 16 17 17 21 22 23 23 24 24 24 25 25 26 27 28 28 28 28 29 31 35 3 Preliminary EMC326SP16AJ 2Mx16 CellularRAM List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Functional Block Diagram - 2 meg x 16 ............................................................................................................... Power-Up Initialization Timing ............................................................................................................................. READ Operation (ADV# LOW) ............................................................................................................................ WRITE Operation (ADV# LOW) ........................................................................................................................... Page Mode READ Operation (ADV# LOW) ......................................................................................................... Burst Mode READ (4-word burst)......................................................................................................................... Burst Mode WRITE (4-word burst)........................................................................................................................ Refresh Collision During Variable-Latency READ Operation ............................................................................... Wired or WAIT Configuration ............................................................................................................................. Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation ............................ Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation .............................. Register READ, Asynchronous Mode, Followed by READ ARRAY Operation .................................................... Register READ, Synchronous Mode, Followed by READ ARRAY Operation ...................................................... Load Configuration Register ................................................................................................................................ Read Configuration Register ............................................................................................................................... Bus Configuration Register Definition .................................................................................................................. WAIT Configuration During Burst Operation ........................................................................................................ Latency Counter (Variable Initial Latency, No Refresh Collision) ......................................................................... Latency Counter (Fixed Latency) ........................................................................................................................ Refresh Configuration Register Mapping ............................................................................................................. AC Input/Output Reference Waveform ................................................................................................................ AC Output Load Circuit ........................................................................................................................................ Initialization Period .............................................................................................................................................. DPD Entry and Exit Timing Parameters ............................................................................................................... Asynchronous READ ........................................................................................................................................... Asynchronous READ Using ADV# ....................................................................................................................... PAGE MODE READ ........................................................................................................................................... Single-Access Burst READ Operation - Variable Latency .................................................................................... 4-Word Burst READ Operation - Variable Latency ............................................................................................... Single-Access Burst READ Operation - Fixed Latency ........................................................................................ 4-Word Burst READ Operation - Fixed Latency ................................................................................................... READ Burst Suspend .......................................................................................................................................... Burst READ at End-of-Row (Wrap off) ................................................................................................ Burst READ Row Boundary Crossing .................................................................................................................. CE# - Controlled Asychronous WRITE ................................................................................................................ LB#/UB# - Controlled Asychronous WRITE ......................................................................................................... WE# - Controlled Asychronous WRITE ............................................................................................................... Asynchronous WRITE Using ADV# ..................................................................................................................... Burst WRITE Operation - Variable Latency Mode ................................................................................................ Burst WRITE Operation - Fixed Latency Mode .................................................................................................... Burst WRITE at End-of-Row (Wrap off) ............................................................................................................... Burst WRITE Row Boundary Crossing ................................................................................................................ Burst WRITE Followed by Burst READ ................................................................................................................ Burst READ Interrupted by Burst READ or WRITE .............................................................................................. Burst WRITE Interrupted by Burst WRITE or READ - Variable Latency Mode ..................................................... Burst WRITE Interrupted by Burst WRITE or READ - Fixed Latency Mode ......................................................... Asynchronous WRITE Followed by Burst READ ................................................................................................. Asynchronous WRITE (ADV# LOW) Followed by Burst READ ........................................................................... Burst READ Followed by Asynchronous WRITE (WE# - Controlled) ................................................................... Burst READ Followed by Asynchronous WRITE Using ADV# ............................................................................. Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW ............................................................. Asynchronous WRITE Followed by Asynchronous READ ................................................................................... 6 9 10 11 11 12 13 14 15 17 18 19 20 21 21 22 24 25 26 27 30 30 35 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 4 Preliminary EMC326SP16AJ 2Mx16 CellularRAM List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: PIN Descriptions ...................................................................................................................................................... Bus Operations ......................................................................................................................................................... Sequence and Burst Length ..................................................................................................................................... Drive Strength .......................................................................................................................................................... Variable Latency Configuration Codes...................................................................................................................... Fixed Latency Configuration Codes.......................................................................................................................... Address Patterns for PAR(RCR[4] =1)...................................................................................................................... Device Identification Register Mapping .................................................................................................................... Absolute Maximum Ratings ..................................................................................................................................... Electrical Characteristics and Operating Conditions ................................................................................................. Deep Power-Down Specifications ............................................................................................................................ Capacitance ............................................................................................................................................................. Asynchronous READ Cycle Timing Requirements ................................................................................................... Burst READ Cycle Timing Requirements ................................................................................................................. Asynchronous WRITE Cycle Timing Requirements ................................................................................................. Burst WRITE Cycle Timing Requirements ............................................................................................................... Initialization and DPD Timing Parameters ................................................................................................................ 7 8 23 24 25 26 28 28 29 29 30 30 31 32 33 34 35 5 Preliminary EMC326SP16AJ 2Mx16 CellularRAM General Description CellularRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications. The 32Mb CellularRAM device has a DRAM core organized as 2 Meg x 16 bits. These devices include an industry-standard burst mode Flash interface that dramatically increase read/write bandwidth compared with other low-power SRAM or Pseudo SRAM offering. To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device READ/WRITE performance. Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. 32Mb CellularRAM products include three mechanisms to minimize standby current. Partial array refresh (PAR) enables the system to limit refresh to only that part of the DRAM array that contains essential data. Temperature compensated refresh (TCR) uses an onchip sensor to adjust the refresh rate to match the device temperature-the refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep power-down (DPD) enables the system to halt the refresh operation altogether when no vital information is stored in the device. The system configurable refresh mechanisms are accessed through the RCR. This 32Mb CellularRAM devices is compliant with the industry-standard CellularRAM 1.5 feature set established by the CellularRAM Workgroup. It includes support for both variable and fixed latency, with three output-device drive-strength settings, additional wrap options, and a device ID register (DIDR). Figure 1 : Functional Block Diagram - 2 meg x 16 A[20:0] Address Decode Logic Refresh Configuration Register (RCR) 2,048K x 16 DRAM MEMORY ARRAY Input Output MUX and Buffers DQ[7:0] DQ[15:8] Device ID Register (DIDR) Bus Configuration Register (BCR) CLK CE# WE# OE# ADV# CRE LB# UB# WAIT Control Logic Internal External Note: Functional block diagrams illustrate simplified device operation. See pin descriptions(Table 1); Bus operations table(Table 2); and timing diagrams for detailed information. 6 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Table 1 : PIN Descriptions Symbol Type Descriptions Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the BCR or the RCR. Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is active. CLK is static LOW during asynchronous access READ and WRITE operations and during PAGE READ ACCESS operations. Address valid: Indiates that a valid address is present on the address inputs. Addresses can be latched on the rising edge of ADV# during asynchronous READ and WRITE operations. ADV# can be held LOW during asynchronous READ and WRITE operations. Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ operations access the RCR, BCR, or DIDR. Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby or deep power-down mode. Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a configuration register or to the memory array. Lower byte enable. DQ[7:0] Upper byte enable. DQ[15:8] A[20:0] Input CLK (Note1) Input ADV# (Note1) Input CRE Input CE# Input OE# Input WE# LB# UB# DQ[15:0] Input Input Input Input/Output Data inputs/outputs. Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is also asserted at the end of a row unless wrapping within the burst length. WAIT is asserted and should be ignored during asynchronous and page mode operations. WAIT is High-Z when CE# is HIGH. Reserved for future use. Device power supply: (1.70V~1.95V) Power supply for device core operation. I/O power supply: (1.70V~1.95V) Power supply for input/output buffers. Vss must be connected to ground. VssQ must be connected to ground. WAIT (Note1) Output RFU Vcc VccQ Vss VssQ Supply Supply Supply Supply Note: 1. When using asynchronous mode or page mode exclusively, CLK and ADV# inputs can be tied to Vss. WAIT will be asserted but should be ignored during asynchronous and page mode operations. 7 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Table 2: Bus Operations Asynchfonous Mode BCR[15]=1 Read Write Standby No operation Configuration register write Configuration register read DPD Burst Mode BCR[15]=0 Async read Async write Standby No operation Initial burst read Initial burst write Burst continue Burst suspend Configuration register write Configuration register read DPD Power Active Active Standby Idle Active CLK1 ADV# CE# L L L L L L L X X L L L H L L OE# L X X X H WE# H L X X L CRE L L L L H UB#/ LB# L L X X X WAIT2 Low-z Low-z High-z Low-z Low-z DQ[15:0]3 Data out Data in High-z X High-z Config. Reg.out High-z 7 Note 4 4 5, 6 4, 6 Active Deep Power-down Power Active Active Standby Idle Active Active Active Active Active L L L L H H L Low-z L X H X X X X UB#/ LB# L L X X L X L X X High-z CLK1 ADV# CE# L L L L L L X X L L H X X L L L H L L L L L L OE# L X X X X H X H H WE# H L X X H L X X L CRE L L L L L L X X H WAIT2 Low-z Low-z High-z Low-z Low-z Low-z Low-z Low-z Low-z DQ[15:0]3 Data out Data in High-z X X X Data out or Data in High-z High-z Config. Reg.out High-z Note 4, 8 4 5, 6 4, 6 4, 9 4, 9 4, 9 4, 9 9, 10 Active Deep Power-down L L L H H L Low-z 9, 10 L X H X X X X High-z 7 Note: 1. CLK must be LOW during async read and async write modes; and to achieve standby power during standby and DPD modes. CLK must be static (HIGH or LOW) during burst suspend. 2. The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are affected. 4. The device will consume active power in this mode whenever addresses are changed. 5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. VIN = VccQ or 0V; all device pins must be static (unswitched) in order to achieve standby current. 7. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is maintained until CE# transitions from HIGH to LOW. 8. When the BCR is configured for sync mode, sync READ and WRITE, and async WRITE are supported by EMLSI. 9. Burst mode operation is initialized through the bus configuration register (BCR[15]). 10. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word burst (as indicated by WAIT). 8 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Functional Description In general, CellularRAM devices are high-density alternatives to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The 32Mb device contains a 33,554,432-bit DRAM core, organized as 2,097,152 addresses by 16 bits.The device implements the same high-speed bus interface found on burst mode Flash products. The CellularRAM bus interface supports both asynchronous and burst mode transfers. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. Power-Up Initialization 32Mb CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will configure the BCR and the RCR with their default settings. (See Figure 16 and 20) Vcc and VccQ must be applied simultaneously. When they reach a stable level at or above 1.7V, the device will require 150s to complete its self-initialization process. During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. Figure 2: Power-Up Initialization Timing Vcc=1.7V Vcc VccQ tPU 150s Device Initialization Device ready for normal operation 9 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Bus Operating Modes 32Mb CellularRAM products incorporate a burst mode interface found on Flash products targeting low-power, wireless applications. This bus interface supports asynchronous, page mode, and burst mode read and write transfers. The specific interface supported is defined by the value loaded into the BCR. Page mode is controlled by the refresh configuration register (RCR[7]). Asynchronous Mode CellularRAM products power up in the asynchronous operating mode.This mode uses the industry- standard SRAM control bus (CE#, OE#, WE#, and LB#/UB#). READ operations (Figure 3) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations (Figure 4) occur when CE#, WE#, and LB#/UB# are driven LOW. During asychronous WRITE operations, the OE# level is a "Don't care", and WE# will override OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asychronous operations (page mode disabled) can either use the ADV# input to latch the address, or ADV# can be driven LOW during the entire READ/ WRITE operation. During asychronous operation, the CLK input must be held static LOW. WAIT will be driven while the device is enabled and its state should be ignored. WE# LOW time must be limited to tCEM Figure 3: READ Operation (ADV# LOW) CE# OE# WE# Address Address Valid DATA Data Valid LB#/UB# tRC = READ Cycle Time Don't Care Note: ADV# must remain Low for PAGE MODE operation. 10 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 4: WRITE Operation (ADV# LOW) CE# OE# < tCEM WE# Address Address Valid DATA Data Valid LB#/UB# tWC = WRITE Cycle Time Don't Care Page Mode Read Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low-order address. Addresses A[3:0] are used to determine the members of the 16-address CellularRAM page. Any change in addresses A[4] or higher will initiate a new tAA access time. Figure 5 shows the timing for a page mode access. Page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. WRITE operations do not include comparable page mode functionality. During asynchronous page mode operation, the CLK input must be held LOW. CE# must be driven HIGH upon completion of a page mode access. WAIT will be driven while the device is enabled and its state should be ignored. Page mode is enabled by setting RCR[7] to HIGH. ADV# must be driven LOW during all page mode READ accesses. Due to refresh considerations, CE# must not be LOW longer than tCEM. Figure 5: Page Mode READ Operation (ADV# LOW) tCEM CE# OE# WE# Address Add0 tAA Add1 Add2 Add3 tAPA D0 tAPA D1 tAPA D2 D3 DATA LB#/UB# Don't Care 11 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Burst Mode Operation Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is latched on the rising edge of the next clock that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH, Figure 6) or a WRITE (WE# = LOW, Figure 7). Figure 6: Burst Mode READ (4-word burst) CLK A[20:0] Address Valid ADV# Latency Code 2 (3 clocks) CE# OE# WE# WAIT DQ[15:0] D0 D1 D2 D3 LB#/UB# READ Burst Identified (WE# = HIGH) Don't Care Undefined Note: Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency; Latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. Diagram in the figure 6 is representative of variable latency with no refresh collision or fixed-latency access. 12 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 7: Burst Mode WRITE (4-word burst) CLK A[20:0] Address Valid ADV# Latency Code 2(3 clocks) CE# OE# WE# WAIT DQ[15:0] D0 D1 D2 D3 LB#/UB# WRITE Burst Identified (WE# = LOW) Don't Care Note: Non-default BCR settings for burst mode WRITE (4-word burst): Fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight, sixteen, or thirty-two words. Continuous bursts have the ability to start at a specified address and burst to the end of the 128-word row. The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between the processor and CellularRAM device. The initial latency for READ operations can be configured as fixed or variable (WRITE operations always use fixed latency). Variable latency allows the CellarRAM to be configured for minimum latency at high clock frequencies, but the controller must monitor WAIT to detect any conflict with refresh cycles. Fixed latency outputs the first data word after the worst-case access delay, including allowance for refresh collisions. The initial latency time and clock speed determine the latency count setting. Fixed latency is used when the controller cannot monitor WAIT. Fixed latency also provides improved performance at lower clock frequencies. The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data is to be transferred into (or out of ) the memory. WAIT will again be asserted at the boundary of the 128-word row, unless wrapping within the burst length. To access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be suspended. Bursts are suspended by stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while the burst is suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT output will continue to be active, and as a result no other devices should directly share the WAIT connection to the controller. To continue the burst sequence, OE# is taken LOW, then CLK is restarted after valid data is available on the bus. The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. If a burst suspension will cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and the burst restarted with a new CE# LOW / ADV# LOW cycle. 13 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Mixed-Mode Operation The device supports a combination of synchronous READ and asynchronous READ and WRITE operations when the BCR is configured for synchronous operation. (Some vendors also support asychronous READ.) The asynchronous READ and WRITE operations require that the clock (CLK) remain LOW during the entire sequence. The ADV# signal can be used to latch the target address, or it can remain LOW during the entire WRITE operation. CE# can remain LOW when transitioning between mixed-mode operations with fixed latency enabled; however, the CE# LOW time must not exceed tCEM. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash memory controllers. See Figure 47 for the "Asychronous WRITE Followed by Burst READ"timing diagram. WAIT Operation The WAIT output on a CellularRAM device is typically connected to a shared, system-level WAIT signal. (See Figure 9.) The shared WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. Figure 9: Wired or WAIT Configuration CellularRAM WAIT READY WAIT Processor Other Device WAIT Other Device External Pull-Up/ Pull-Down Resistor When a READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires additional time before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges. During a burst cycle, CE# must remain asserted until the first data is valid. Bringing CE# HIGH during WAIT cycles may cause data corruption. When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for READ operations launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock cycles until the refresh has completed. (See Figure 8) When the refresh operation has completed, the READ operation will continue normally. WAIT will be asserted but should be ignored during asynchronous READ and WRITE, and page READ operations. By using fixed initial latency (BCR[14] = 1), this CellularRAM device can be used in burst mode without monitoring the WAIT signal. However, WAIT can still be used to determine when valid data is available at the start of the burst and at the end of row. If WAIT is not monitored, the controller must stop burst accesses at row boundaries on its own. LB#/UB# Operation The LB# enable and UB# enable signals support byte-wide data WRITEs. During WRITE operations, any disabled bytes will not be transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. LB# and UB# must be LOW during READ cycles. When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW. 14 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 8: Refresh Collision During Variable-Latency READ Operation VIH CLK VIL VIH A[20:0] VIL VIH ADV# VIL VIH VIL VIH OE# VIL VIH VIL VIH LB#/UB# VIL VOH WAIT VOL VOH DQ[15:0] VOL High-Z Valid Address CE# WE# D0 D1 D2 D3 Additional WAIT states inserted to allow refresh completion Don't Care Undefined Note: Non-default BCR settings for refresh collision during variable-latency READ operation: Latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 15 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion of a READ or WRITE operation, or when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the address or control inputs. Temperature Compensated Refresh Temperature compensated refresh (TCR) allows for adequate refresh at different temperatures. This CellularRAM device includes an on-chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. The device continually adjusts the refresh rate to match that temperature. Partial Array Refresh Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, onehalf array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map. (See Table 11) READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new portions are available immediately upon writing to the RCR. Deep Power-Down Operation Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been reenabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. During this 150s period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. DPD can be enabled by writing to the RCR using CRE or the software access sequence; DPD starts when CE# goes HIGH. DPD is disabled the next time CE# goes LOW and stays LOW for at least 10s. 16 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Registers Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up, and can be updated any time the devices are operating in a standby state. A DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device configuration. The DIDR is read-only. Access Using CRE The registers can be accessed using either a synchronous or an asynchronous operation when the control register enable (CRE) input is HIGH. (See Figure 10 through 13) When CRE is LOW, a READ or WRITE operation will access the memory array. The configuration register values are written via addresses A[20:0]. In an asynchronous WRITE, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are "Don't Care". The BCR is accessed when A[19:18] are 10b; the RCR is accessed when A[19:18] are 00b. The DIDR is read when A[19:18] are 01b. For reads, address inputs other than A[19:18] are "Don't Care", and register bits 15:0 are output on DQ[15:0]. Immediately after performing a configuration register READ or WRITE operation, reading the memory array is highly recommended. Figure 10: Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation A[20:0] (except A[19:18]) OPCODE tAVS Select control register Address tAVH Address A[19:18]1 CRE tAVS tAVH ADV# tVP CE# Initiate control register access tCW OE# tWP WE# Write address bus value to control register tCPH LB#/UB# DQ[15:0] Data Valid Don't Care Note: 1. A[19:18] = 00b to load RCR, and 10b to load BCR. 17 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 11: Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation CLK Latch control register value A[20:0] (except A[19:18]) OPCODE tSP tHD Latch control register address Address A[19:18] 2 Address tSP tHD CRE tSP ADV# tCBPH Note 3 tHD tCSP CE# OE# tSP tHD WE# LB#/UB# tCEW WAIT High-Z High-Z DQ[15:0] Data Valid Don't Care Note: 1. Non-default BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: Latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay. 2. A[19:18] = 00b to load RCR, and 10b to load BCR. 3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. 18 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 12: Register READ, Asynchronous Mode, Followed by READ ARRAY Operation A[20:0] (except A[19:18]) tAVS Select Register Address tAVH Address tAA tAVH A[19:18]1 CRE tAVS tAA ADV# tVP CE# tAADV tCPH Initiate register access tCO tHZ OE# tOE WE# tOLZ tLZ LB#/UB# tLZ DQ[15:0] CR Valid Data Valid tBHZ tBA tOHZ Don't Care Undefined Note: A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR. 19 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 13: Register READ, Synchronous Mode, Followed by READ ARRAY Operation (WE# HIGH) CLK Latch control register value A[20:0] (except A[19:18]) tSP A[19:18]2 tSP CRE tHD tSP ADV# tHD tCSP CE# tABA Note 3 Latch control register address Address Address tHD tCBPH tHZ OE# tOHZ WE# tSP LB#/UB# tCW WAIT High-Z tBOE tHD tACLK tOLZ tKOH High-Z DQ[15:0] CR Valid Data Valid Don't Care Undefined Note: 1. Non-default BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR. 3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. 20 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Software Access Software access of the registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configuration registers can be modified and all registers can be read using the software sequence. The configuration registers are loaded using a four-step sequence consisting of two asynchronous READ operations followed by two asynchronous WRITE operations.(See Figure 14.) The read sequence is virtually identical except that an asynchronous READ is performed during the fourth operation. (See Figure 15.) The address used during all READ and WRITE operations is the highest address of the CellularRAM device being accessed (1FFFFFh); the contents of this address are not changed by using this sequence. The data value presented during the third operation (WRITE) in the sequence defines whether the BCR, RCR, or the DIDR is to be accessed. If the data is 0000h, the sequence will access the RCR; if the data is 0001h, the sequence will access the BCR; if the data is 0002h, the sequence will access the DIDR. During the fourth operation, DQ[15:0] transfer data in to or out of bits 15:0 of the registers. The use of the software sequence does not affect the ability to perform the standard (CRE-controlled) method of loading the configuration registers. However, the software nature of this access mechanism eliminates the need for CRE. If the software mechanism is used, CRE can simply be tied to Vss. The port line often used for CRE control purposes is no longer required. Figure 14: Load Configuration Register READ Address ADDRESS Max READ ADDRESS Max WRITE ADDRESS Max WRITE ADDRESS Max CE# OE# WE# LB#/UB# DATA XXXXh XXXXh RCR : 0000h BCR : 0001h CR Value In Don't Care Figure 15: Read Configuration Register READ Address ADDRESS Max READ ADDRESS Max WRITE ADDRESS Max READ ADDRESS Max CE# OE# WE# LB#/UB# DATA XXXXh XXXXh RCR : 0000h BCR : 0001h DIDR : 0002h CR Value In Don't Care 21 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Bus Configuration Register The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 16 describes the control bit BCR. At power-up, the BCR is set to 9D1Fh. The BCR is accessed with CRE HIGH and A[19:18] = 10b, or through the register access software sequence with DQ = 0001h on the third cycle. Figure 16: Bus Configuration Register Definition A[20] A[19:18] A[17:16] A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 20 Reserved 19-18 Register Select 17-16 Reserved 15 14 13 12 Latency Counter 11 10 9 8 7 6 5 4 3 2 1 0 Operating Initial Mode Latency WAIT WAIT Drive Burst Burst Reserved Reserved Reserved Polarity Configuration(WC) Strength Wrap(BW)* Length(BL)* All must be set to "0" Must be set to "0" Must be set to "0" Must be set to "0" Must be set to "0" BCR[14] 0 1 Initial Access Latency Variable (default) Fixed BCR[3] 0 1 Burst Wrap (Note 1) Burst wraps within the burst length Burst no wrap (default) BCR[5] BCR[4] Drive Strength BCR[13] BCR[12] BCR[11] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Latency Counter Code 8 Code 1 - Reserved Code 2 Code 3 (default) Code 4 Code 5 Code 6 Code 7 - Reserved BCR[10] 0 1 BCR[15] 0 1 Operating Mode Synchronous burst access mode Asynchronous access mode (default) 0 0 1 1 0 1 0 1 Full 1/2 (default) 1/4 Reserved BCR[8] 0 1 WAIT Polarity Active LOW Active HIGH (default) WAIT Configuration Asserted during delay Asserted one data before delay(default) BCR[2] BCR[1] BCR[0] Burst Length (Note 1) 0 0 0 1 1 0 1 1 0 1 Others 1 0 1 0 1 4 words 8 words 16 words 32 words Continuous burst (default) Reserved BCR[19] BCR[18] Register Select 0 1 0 0 0 1 Select RCR Select BCR Select DIDR Note: 1. Burst wrap and length apply to both READ and WRITE operations. 22 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Burst Length (BCR[2:0]) Default = Continuous Burst Burst lengths define the number of words the device outputs during burst READ and WRITE operations. The device supports a burst length of 4, 8, 16, or 32 words. The device can also be set in continuous burst mode where data is accessed sequentially up to the end of row. Burst Wrap (BCR[3]) Default = No Wrap The burst-wrap option determines if a 4, 8, 16, or 32 word READ or WRITE burst wraps within the burst length, or steps through sequential addresses. If the wrap option is not enabled, the device accesses data from sequential addresses up to the end of the row. Table 3: Sequence and Burst Length BURST Wrap Starting Address 4 Word Burst Length Linear 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8 Word Burst Length Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 16 Word Burst Length Linear 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 ... 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 32 Word Burst Length Linear 0-1-2 ... 29-30-31 1-2-3 ... 30-31-0 2-3-4 ... 31-0-1 3-4-5 ... 0-1-2 4-5-6 ... 1-2-3 5-6-7 ... 2-3-4 6-7-8 ... 3-4-5 7-8-9 ... 4-5-6 ... 14-15-16-...-11-12-13 15-16-17...-12-13-14 ... 30-31-0-...-27-28-29 31-0-1-... -28-29-30 Continuous Burst Linear 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-... 5-6-7-8-9-10-11-... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13-... ... 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-... ... 30-31-32-33-34-... 31-32-33-34-35-... 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-... 5-6-7-8-9-10-11-... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13-... ... 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-... ... 30-31-32-33-34-35-36-... 31-32-33-34-35-36-37-... BCR[3] Wrap Decimal 0 1 2 3 4 5 6 0 Yes 7 ... 14 15 ... 30 31 0 1 2 3 4 5 6 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-20 6-7-8-9-10-11-12-13-14-15-16-17-18-19-20-21 ... 14-15-16-17-18-...-23-24-25-26-27-28-29 15-16-17-18-19-...-24-25-26-27-28-29-30 0-1-2-...-29-30-31 1-2-3-...-30-31-32 2-3-4-...-31-32-33 3-4-5-...-32-33-34 4-5-6-...-33-34-35 5-6-7-...-34-35-36 6-7-8-...-35-36-37 7-8-9-...-36-37-38 ... 14-15-16-...43-44-45 15-16-17-...-44-45-46 ... 30-31-32-...-59-60-61 31-32-33-...-60-61-62 1 No 7 ... 14 15 ... 30 31 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-22 23 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. The reduced-strength options are intended for stacked chip (Flash + CelllularRAM) environments when there is a dedicated memory bus. The reduced-drive-strength option minimizes the noise generated on the data bus during READ operations. Full output drive strength should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Outputs are configured at half-drive strength during testing. See Table 4 for additional information. Table 4: Drive Strength BCR[5] 0 0 1 1 BCR[4] 0 1 0 1 Drive Strength Full 1/2 (default) 1/4 Impedance Typ ( 25~30 50 100 Reserved ) Use Recommendation CL = 30pF to 50pF CL = 15pF to 30pF 104 MHz at light load CL = 15pF or lower WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively. When A8 = 1, the WAIT signal transitions one clock period prior to the data bus going valid or invalid. (See Figure 17.) WAIT Polarity (BCR[10]) Default = WAIT Active HIGH The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state. Figure 17: WAIT Configuration During Burst Operation CLK BCR[8] = 0 WAIT Data valid in current cycle BCR[8] = 1 WAIT Data valid in next cycle DQ[15:0] D0 D1 D2 D3 End of row Don't Care Note: Non-default BCR setting: WAIT active LOW. 24 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Latency Counter (BCR[13:11]) Default = Three Clock Latency The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred. For allowable latency codes, see Tables 5 and 6, respectively, and Figures 18 and 19, respectively. Initial Access Latency (BCR[14]) Default = Variable Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must be monitored to detect delays caused by collisions with refresh operations. Fixed initial access latency outputs the first data at a consistent time that allows for worst-case refresh collisions. The latency counter must be configured to match the initial latency and the clock frequency. It is not necessary to monitor WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency counter. (See Table 6 and Figure 19) Table 5: Variable Latency Configuration Codes BCR[13:11] 010 011 100 Others Latency Configuration Code 2 (3 clocks) 3 (4 clocks)-default 4 (5 clocks) Reserved Latency 1 Normal 2 3 4 Refresh Collision 4 6 8 Max Input CLK Frequency (MHz) 133 66(15ns) 104 66(15ns) 83 52(19.2ns) 83(12ns) - 104(9.62ns) 104(9.62ns) 133(7.5ns) - Note: 1. Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle. Figure18: Latency Counter (Variable Initial Latency, No Refresh Collision) VIH CLK VIL VIH A[20:0] VIL VIH Valid Address ADV# VIL DQ[15:0] VOH VOL Code 2 Valid Output (default) Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Don't Care Valid Output Valid Output Undefined DQ[15:0] VOH VOL Code 3 25 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Table 6: Fixed Latency Configuration Codes BCR[13:11] 010 011 100 101 110 000 others Latency Configuration Code 2 (3 clocks) 3 (4 clocks)-default 4 (5 clocks) 5 (6 clocks) 6 (7 clocks) 8 (9 clocks) Reserved Max Input CLK Frequency (MHz) Latency Count (N) 2 3 4 5 6 8 -133 33(30ns) 52(19.2ns) 66(15ns) 75(13.3ns) 104(9.62ns) 133(7.5ns) 104 33(30ns) 52(19.2ns) 66(15ns) 75(13.3ns) 104(9.62ns) 83 33(30ns) 52(19.2ns) 66(15ns) 75(13.3ns) 83(12ns) - Figure 19: Latency Counter (Fixed Latency) N-1 Cycles CLK VIH VIL VIH Cycle N tAA Valid Address tAADV A[20:0] VIL VIH ADV# VIL VIH tCO tACLK Valid Output tSP tHD Valid Output Valid Output Valid Output Valid Output CE# VIL VOH DQ[15:0] (READ) V OL DQ[15:0] (WRITE) V OL VOH Valid Input Valid Input Valid Input Valid Input Valid Input Undefined Burst Identified (ADV# = LOW) Don't Care Operating Mode (BCR[15]) Default = Asynchronous Operation The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation. 26 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Refresh Configuration Register The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Figure 20 describes the control bits used in the RCR. At power-up, the RCR is set to 0010h. The RCR is accessed with CRE HIGH and A[19:18] = 00b; or through the register access software sequence with DQ = 0000h on the third cycle. Figure 20: Refresh Configuration Register Mapping Address Bus A[20] A[19:18] A[17:8] A7 A6 A5 A4 A3 A2 A1 A0 20 Reserved 19-18 Register Select 17-8 Reserved 7 Page 6 Reserved 5 4 3 Reserved 2 1 PAR 0 DPD All must be set to "0" All must be set to "0" Setting is ignored (Default 00b) Must be set to "0" RCR[19] 0 1 0 RCR[18] 0 0 1 Register Select Select RCR Select BCR Select DIDR RCR[2] 0 0 0 0 1 RCR[1] 0 0 1 1 0 0 1 1 RCR[0] 0 1 0 1 0 1 0 1 Refresh Coverage Full array (default) Bottom 1/2 array Bottom 1/4 array Bottom 1/8 array None of array Top 1/2 array Top 1/4 array Top 1/8 array RCR[7] 0 1 Page Mode Enable/Disable Page Mode Disable (default) Page Mode Enable 1 1 1 RCR[4] 0 1 Deep Power-Down DPD Enable DPD Disable (default) 27 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Partial Array Refresh (RCR[2:0] Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, onequarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map. Table 7: Address Patterns for PAR (RCR[4] = 1) RCR[2] 0 0 0 0 1 1 1 1 RCR[1] 0 0 1 1 0 0 1 1 RCR[0] 0 1 0 1 0 1 0 1 Active Section Full Die One-half die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die Address Space 000000h-1FFFFFh 000000h-0FFFFFh 000000h-07FFFFh 000000h-03FFFFh 0 100000h-1FFFFFh 180000h-1FFFFFh 1C0000h-1FFFFFh Size 2 Meg x 16 1 Meg x 16 512 K x 16 256 K x 16 0 Meg x 16 1 Meg x 16 512 K x 16 256 K x 16 Density 32Mb 16Mb 8Mb 4Mb 0Mb 16Mb 8Mb 4Mb Deep Power-Down (RCR[4]) Default = DPD Disabled The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. Deep power-down is enabled by setting RCR[4] = 0 and taking CE# HIGH. DPD can be enabled using CRE or the software sequence to access the RCR. Taking CE# LOW for at least 10s disables DPD and sets RCR[4] = 1; it is not necessary to write to the RCR to disable DPD. BCR and RCR values (other than RCR[4]) are preserved during DPD. Page Mode Operation (RCR[7]) Default = Disabled The page mode operation bit determines whether page mode is enabled for asynchronous READ operations. In the power-up default state, page mode is disabled. Device Identification Register The DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device configuration. Table 8 describes the bit fields in the DIDR. This register is read-only. The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the register access software sequence with DQ = 0002h on the third cycle. Table 8: Device Identification Register Mapping Bit Field Field name DIDR[15] Row Length Length Bit Setting 0b DIDR[14:11] Device version Version 2nd Bit Setting 0001b DIDR[10:8] Device density Density 32Mb Bit Setting 001b DIDR[7:5] CellularRAM generation Generation CR 1.5 Bit Setting 010b DIDR[4:0] Vendor ID Vendor EMLSI Bit Setting 01010b Options 128 words 28 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Electrical Characteristics Table 9: Absolute Maximum Ratings Parameter Voltage to any pin except Vcc, VccQ relative to Vss Voltage on Vcc supply relative to Vss Voltage on VccQ supply relative to Vss Storage temperature (plastic) Operating temperature (case) Wireless Soldering temperature and time 10s (solder ball only) Rating -0.50V to VccQ + 0.3V -0.2V to +2.45V -0.2V to +2.45V -55C to +150C -30C to +85C +260C Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 10: Electrical Characteristics and Operating Conditions Wireless Temperature (-30C < TC < +85C) Description Supply voltage I/O supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current IOH = -0.2mA IOL = +0.2mA VIN = 0 to VccQ OE# = VIH or chip disabled Conditions Vcc VccQ VIH VIL VOH VOL ILI ILO Symbol Min 1.7 1.7 VccQ - 0.4 -0.20 0.80 VccQ Max 1.95 1.95 VccQ + 0.2 0.4 Unit V V V V V Note 1 2 3 3 0.20 VccQ 1 1 V A A Unit mA mA mA mA mA mA mA mA mA mA mA 4 4 4 Operating current Asynchronous random READ/WRITE Asynchronous PAGE READ Initial access burst READ/WRITE Conditions ICC1 ICC1P Symbol 70ns 70ns 133MHz ICC2 104MHz 83MHz 133MHz Typ Max 25 15 40 35 30 35 30 25 40 35 30 140 120 100 Note 4 4 VIN = VccQ or 0V chip enabled, IOUT = 0 Continuous burst READ ICC3R 104MHz 83MHz 133MHz Continuous burst WRITE ICC3W 104MHz 83MHz Standard A A A 5, 6 Standby current VIN = VccQ or 0V, CE# = VccQ ISB Low Power LowLowPower Note: 1. Input signals may overshoot to VccQ + 1.0V for periods less than 2ns during transitions. 2. Input signals may undershoot to Vss - 1.0V for periods less than 2ns during transitions. 3. BCR[5:4] = 01b (default setting of one-half drive strength). 4. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. 5. ISB (max) values measured with PAR set to FULL ARRAY and at +85C. In order to achieve low standby current, all inputs must be driven to either VccQ or Vss. ISB might be slightly higher for up to 500ms after power-up, or when entering standby mode. 6. ISB (typ) is the average ISB at 25C and Vcc = VccQ = 1.8V. This parameter is verified during characterization, and is not 100% tested. 29 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Table 11: Deep Power-Down Specifications Description Deep Power-Down Conditions VIN = VccQ or 0V; Vcc, VccQ = 1.95V; +85C Symbol IZZ Typ - Max 10 Unit A Note: Typical (TYP) IZZ value is tested at Vcc=1.8V, TA=25C and not guaranteed. Table 12: Capacitance Description Input Capacitance Input/Output Capacitance(DQ) Tc = +25C; f = 1 MHz; VIN = 0V Conditions Symbol CIN CIO Min 2.0 3.5 Max 6 6 Unit pF pF Note 1 1 Note: These parameters are verified in device characterization and are not 100% tested. Figure 21: AC Input/Output Reference Waveform VccQ Input1 VssQ VccQ/22 Test Points VccQ/23 Output Note: 1. AC test inputs are driven at VccQ for a logic 1 and VssQ for a logic 0. Input rise and fall times (10% to 90%) <1.6ns. 2. Input timing begins at VccQ/2. 3. Output timing ends at VccQ/2. Figure 22: AC Output Load Circuit Test Points 50-Ohm DUT VccQ/2 30pF Note: All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b). 30 Preliminary EMC326SP16AJ 2Mx16 CellularRAM TIMING REQUIREMENTS Table 13: Asynchronous READ Cycle Timing Requirements All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b). Parameter Address access time ADV# access time Page access time Address hold from ADV# HIGH Address setup to ADV# HIGH LB#/UB# access time LB#/UB# disable to DQ High-Z output LB#/UB# enable to Low-Z output Maximum CE# pulse width CE# LOW to WAIT valid Chip select access time CE# LOW to ADV# HIGH Chip disable to DQ and WAIT High-Z output Chip enable to Low-Z output Output enable to valid output Output hold from address change Output disable to DQ High-Z output Output enable to Low-Z output Page READ cycle time READ cycle time ADV# pulse width LOW Symbol tAA tAADV tAPA tAVH tAVS tBA tBHZ tBLZ tCEM tCEW tCO tCVS tHZ tLZ tOE tOH tOHZ tOLZ tPC tRC tVP 70ns Min 2 5 10 1 7 10 5 3 20 70 5 Max 70 70 20 70 8 4 7.5 70 8 20 8 - Unit ns ns ns ns ns ns ns ns Note 4 1 2 3 s ns ns ns ns ns ns ns ns ns ns ns ns 1 2 1 2 4 Note: 1. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2. 2. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either VOH or VOL. 3. Page mode enabled only. 4. Contact EMLSI for specific timing. 31 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Table 14: Burst READ Cycle Timing Requirements All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b). Parameter Address access time (fixed latency) ADV# access time (fixed latency) Burst to READ access time (variable latency) CLK to output delay Address hold from ADV# HIGH(fixed latency) Burst OE# LOW to output delay CE# HIGH between subsequent burst or mixed mode operations Maximum CE# pulse width CE# or ADV# LOW to WAIT valid CLK period Chip select access time (fixed latency) CE# setup time to active CLK edge Hold time from active CLK edge Chip disable to DQ and WAIT High-Z output CLK rise or fall time CLK to WAIT valid Output HOLD from CLK CLK HIGH or LOW time Output disable to DQ High-Z output Output enable to Low-Z output Setup time to active CLK edge Symbol tAA tAADV tABA tACLK tAVH tBOE tCBPH tCEM tCEW tCLK tCO tCSP tHD tHZ tKHKL tKHTL tKOH tKP tOHZ tOLZ tSP 2 5 1 133MHz Min Max 70 70 35.5 5.5 20 4 7.5 70 7 1.2 5.5 7 - 104MHz Min 2 5 1 9.62 3 2 2 3 3 3 Max 70 70 35.9 7 20 4 7.5 70 8 1.6 7 8 - 83MHZ Min 2 6 1 12 4 2 2 4 3 3 Max 70 70 45 9 20 4 7.5 70 8 1.8 9 8 - Unit Note ns ns ns ns ns ns ns 1 1 s ns ns ns ns ns ns ns ns ns ns ns ns ns 7.5 2.5 1.5 2 3 3 2 3 2 3 Note: 1. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. 2. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2. 3. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either VOH or VOL. 32 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Table 15: Asynchronous WRITE Cycle Timing Requirements Parameter Address and ADV# LOW setup time Address HOLD from ADV# going HIGH Address setup to ADV# going HIGH Address valid to end of WRITE LB#/UB# select to end of WRITE CE# LOW to WAIT valid CE# HIGH between subsequent async operations CE# LOW to ADV# HIGH Chip enable to end of WRITE Data HOLD from WRITE time Data WRITE setup time Chip disable to WAIT High-Z output Chip enable to Low-Z output End WRITE to Low-Z output ADV# pulse width ADV# setup to end of WRITE WRITE cycle time WRITE to DQ High-Z output WRITE pulse width WRITE pulse width HIGH WRITE recovery time Symbol tAS tAVH tAVS tAW tBW tCEW tCPH tCVS tCW tDH tDW tHZ tLZ tOW tVP tVS tWC tWHZ tWP tWPH tWR 70ns Min 0 2 5 70 70 1 5 7 70 0 20 10 5 5 70 70 45 10 0 Max 7.5 8 8 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1 2 2 1 3 Note: 1. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2. 2. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either VOH or VOL. 3. WE# Low time must be limited to tCEM (4s). 33 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Table 16: Burst WRITE Cycle Timing Requirements Parameter Address and ADV# LOW setup time Address HOLD from ADV# HIGH(fixed latency) CE# HIGH between subsequent burst or mixed mode operations Maximum CE# pulse width CE# LOW to WAIT valid Clock period CE# setup to CLK active edge Hold time from active CLK edge Chip disable to WAIT High-Z output CLK rise or fall time Clock to WAIT valid CLK HIGH or LOW time Setup time to activate CLK edge Symbol tAS tAVH tCBPH tCEM tCEW tCLK tCSP tHD tHZ tKHKL tKHTL tKP tSP 0 2 5 1 133MHz Min Max 4 7.5 7 1.2 5.5 - 104MHz Min 0 2 5 1 9.62 3 2 3 3 Max 4 7.5 8 1.6 7 1 12 4 2 3 3 83MHZ Min 0 2 6 Max 4 7.5 8 1.8 9 - Unit Notes ns ns ns 2 2 1 s ns ns ns ns ns ns ns ns ns 7.5 2.5 1.5 3 2 3 Note: 1. tAS required if tCSP > 20ns. 2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. 3. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2. 34 Preliminary EMC326SP16AJ 2Mx16 CellularRAM TIMING DIAGRAMS Figure 23: Initialization Period Vcc(MIN) Vcc, VccQ = 1.7V tPU Device ready for normal operation Figure 24: DPD Entry and Exit Timing Parameters tDPD CE# tDPDX tPU Write RCR[4] = 0 DPD Enabled DPD EXIT Device Initialization Device ready for normal operation Table 17: Initialization and DPD Timing Parameters Symbol tDPD tDPDX tPU Min 150 10 Max Unit s s s 150 35 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 25: Asynchronous READ tRC VIH A[20:0] VIL VIH Valid Address tAA ADV# VIL VIH tCO tHZ CE# VIL VIH tBA tBHZ LB#/UB# VIL VIH tOE tOHZ OE# VIL VIH VIL VOH WE# tOLZ tBLZ tLZ High-Z tCEW High-Z DQ[15:0] VOL VOH Valid Output tHZ High-Z WAIT VOL Don't Care Undefined 36 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 26: Asynchronous READ Using ADV# A[20:0] VIH VIL Valid Address tVPH tAVS tAA tAVH tAADV tVP tCVS tCO tBA tBHZ tHZ ADV# VIH VIL CE# VIH VIL LB#/UB# VIH VIL VIH tOE tOHZ OE# VIL VIH VIL VOH WE# tOLZ tBLZ tLZ High-Z tCEW High-Z DQ[15:0] VOL VOH Valid Output tHZ High-Z WAIT VOL Don't Care Undefined 37 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 27: PAGE MODE READ tRC VIH A[20:4] VIL VIH VIL Valid Address Valid Address Valid Address Valid Address A[3:0] Valid Address tAA tPC ADV# VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tCEM tCO tHZ tBA tBHZ tOE tOHZ CE# LB#/UB# OE# WE# tOLZ tBLZ tAPA tOH Valid Output Valid Output Valid Output Valid Output VOH tLZ High-Z tCEW High-Z DQ[15:0] VOL VOH tHZ High-Z WAIT VOL Don't Care Undefined 38 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 28: Single-Access Burst READ Operation - Variable Latency tCLK VIH tKP tKP CLK VIL tKHKL tSP tHD VIH A[20:0] VIL VIH VIL Valid Address tSP tHD tHD tCEM tCSP tABA tHZ ADV# CE# VIH VIL OE# VIH VIL VIH tBOE tSP tHD tOLZ tOHZ WE# VIL VIH tSP tKHTL tHD LB#/UB# VIL VOH tCEW High-Z WAIT VOL VOH High-Z tACLK High-Z tKOH High-Z DQ[15:0] Valid Output VOL READ Burst Identified (WE# = HIGH) Note: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Don't Care Undefined 39 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 29: 4-Word Burst READ Operation - Variable Latency tKHKL VIH tCLK tKP tKP CLK VIL VIH tSP tHD A[20:0] VIL VIH Valid Address tSP tHD tCEM tCSP tABA tHD tCBPH tHZ tBOE tSP tHD tOLZ tOHZ ADV# VIL VIH CE# VIL VIH OE# VIL VIH WE# VIL VIH tSP tKHTL tHD LB#/UB# VIL VOH tCEW High-Z WAIT High-Z tACLK tKOH Valid Output Valid Output Valid Output Valid Output VOL VOH DQ[15:0] VOL High-Z High-Z READ Burst Identified (WE# = HIGH) Note: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Don't Care Undefined 40 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 30: Single-Access Burst READ Operation - Fixed Latency tCLK VIH tKP tKP CLK VIL VIH tSP Valid Address tAVH tSP tHD tAADV tCEM tCSP tCO tAA tKHKL A[20:0] VIL ADV# VIH VIL tHD tHZ CE# VIH VIL OE# VIH VIL VIH VIL VIH VIL VOH tBOE tSP tHD tOLZ tOHZ WE# tSP tKHTL tHD LB#/UB# tCEW High-Z WAIT DQ[15:0] High-Z tACLK tKOH High-Z VOL VOH VOL High-Z Valid Output READ Burst Identified (WE# = HIGH) Don't Care Undefined Note: 1. Non-default BCR settings: Fixed latency; latency code four (five clocks); WAIT active LOW; WAIT asserted during delay. 41 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 31. 4-Word Burst READ Operation - Fixed Latency tCLK tKHKL tKP tKP CLK VIH VIL tSP tHD A[20:0] VIH Valid Address VIL ADV# VIH VIL tSP tCSP tAVH tHD tAA tAADV tCEM tCO tBOE tSP tHD tOLZ tHD tCBPH tHZ CE# VIH VIL OE# VIH VIL tOHZ WE# VIH VIL LB#/UB# VIH VIL tSP tKHTL tHD WAIT VOH VOL High-Z tCEW High-Z tACLK High-Z Valid Output DQ[15:0] VOH VOL tKOH Valid Output Valid Output Valid Output READ Burst Identified (WE# = HIGH) Don't Care Undefined Note: 1. Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 42 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 32. READ Burst Suspend tCLK VIH Note 2 CLK A[20:0] VIL VIH VIL tSP tHD Valid Address Valid Address ADV# VIH VIL tSP tHD tCEM tCBPH tHz tOHZ tOHZ CE# VIH VIL tCSP Note 3 OE# VIH VIL tSP tHD WE# VIH VIL LB#/UB# VIH VIL tSP tOLZ tBOE tHD WAIT VOH VOL High-Z High-Z tKOH High-Z Valid Output Valid Output Valid Output Valid Output tBOE tOLZ Valid Output Valid Output DQ[15:0] VOH VOL tACLK Don't Care Undefined Note: 1. Non-default BCR settings for READ burst suspend: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. CLK can be stopped LOW or HIGH, but must be static, with no LOW-to-HIGH transitions during burst suspend. 3. OE# can stay LOW during burst suspend. If OE# is LOW, DQ[15:0] will continue to output valid data. 43 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 33. Burst READ at End-of-Row (Wrap Off) VIH CLK VIL VIH tCLK A[20:0] VIL VIH ADV# VIL VIH UB#/LB# VIL VIH tHD Note 2 tCSP CE# VIL VIH OE# VIL VIH WE# DQ[15:0] VIL VOH VOL VOH VOL Valid Output Valid Output End of row tKHTL tHZ tHZ High-Z WAIT tKOH Don't Care Undefined Note: 1. Non-default BCR settings for burst READ at end of row : fixed or variable latency, WAIT active LOW; WAIT asserted during delay. 2. For burst READs, CE# must go HIGH before the second CLK after the WAIT period begins ( befor the second CLK after WAIT asserts with BCR[8]=0, or before the third CLK after WAIT asserts with BCR[8]=1 ). 44 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 34. Burst READ Row boundary crossing CLK VIH VIL tCLK A[20:0] ADV# VIH VIL VIH VIL VIH UB#/LB# VIL VIH VIL CE# OE# VIH VIL VIH VIL WE# tSP VOH tHD End of row Valid output Valid output Valid out DQ[15:0] Valid output VOL VOH tKTHL Note 2 tKOH tKTHL WAIT V OL tKOH Don't Care Note: 1. Non-default BCR settings for burst READ at end of row : fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as solid line) 2. WAIT will be assert for LC or LC + 1 cycles for variables latency, or LC cycles for fixed latency. 45 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 35. CE#-Controlled Asynchronous WRITE tWC A[20:0] VIH VIL Valid Address tAS tAW tWR tCW tCPH ADV# VIH VIL VIH VIL CE# LB#/UB# VIH VIL tBW OE# VIH VIL tWPH tWP WE# DQ[15:0] IN DQ[15:0] OUT WAIT VIH VIL VIH tDW High-Z Valid Input tDH VIL VOH VOL VOH VOL tLZ tWHZ tCEW High-Z tHZ High-Z Don't Care 46 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 36. LB#/UB#-Controlled Asynchronous WRITE tWC A[20:0] VIH Valid Address VIL tAW tAS tCW tWR ADV# VIH VIL CE# VIH VIL LB#/UB# VIH VIL tBW OE# VIH VIL tWPH tWP WE# DQ[15:0] IN DQ[15:0] OUT WAIT VIH VIL VIH tDW High-Z Valid Input tDH VIL VOH VOL VOH VOL tLZ tWHZ tCEW High-Z tHZ High-Z Don't Care 47 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 37. WE#-Controlled Asynchronous WRITE tWC A[20:0] VIH Valid Address VIL tAW tWR ADV# VIH VIL CE# VIH VIL tCW LB#/UB# VIH VIL VIH VIL tBW tAS tWPH tWP OE# WE# DQ[15:0] IN DQ[15:0] OUT WAIT VIH VIL VIH VIL VOH VOL VOH VOL tDW High-Z Valid Input tDH tLZ tWHZ tOW tHZ High-Z tCEW High-Z Don't Care 48 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 38. Asynchronous WRITE Using ADV# A[20:0] VIH Valid Address VIL tAVS tVPH tVP tAS tAS tCVS tAVH tVS tAW tCW ADV# VIH VIL VIH CE# VIL VIH VIL VIH tBW LB#/UB# OE# WE# DQ[15:0] IN DQ[15:0] OUT WAIT VIL VIH VIL VIH tWP tWPH tDW High-Z Valid Input tDH VIL VOH VOL VOH VOL tLZ tWHZ tOW tHZ High-Z tCEW High-Z Don't Care 49 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 39. Burst WRITE Operation - Variable Latency Mode tCLK tKHKL tKP tKP CLK VIH VIL tSP tHD A[20:0] VIH Valid Address VIL tAS3 tSP tAS 3 ADV# VIH VIL tHD tHD tCEM tCBPH CE# VIH VIL tCSP OE# VIH VIL tSP tHD WE# VIH VIL tSP LB#/UB# VIH VIL VOH VOL ViH D1 ViL tHD tHZ High-Z tCEW High-Z Note 2 tKHTL WAIT tSP tHD D2 D3 D0 DQ[15:0] WRITE Burst Identified (WE# = Low) Don't Care Note: 1. Non-default BCR settings for burst WRITE operation in variable latency mode: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay; burst length four; burst wrap enabled. 2. WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]). 3. tAS required if tCSP > 20ns. 50 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 40. Burst WRITE Operation - Fixed Latency Mode tCLK tKHKL tKP tKP CLK VIH VIL tSP Valid Address A[20:0] VIH VIL tAS3 tSP tAS3 tCSP tHD tAVH ADV# VIH VIL tHD tCEM tCBPH CE# VIH VIL OE# VIH VIL tSP tHD WE# VIH VIL tSP LB#/UB# WAIT VIH VIL VOH VOL tHD tHZ High-Z tCEW High-Z Note 2 tKHTL tSP D1 tHD D2 D3 D0 DQ[15:0] VIH VIL WRITE Burst Identified (WE# = Low) Don't Care Note: 1. Non-default BCR settings for burst WRITE operation in fixed latency mode: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay; burst length four; burst wrap enabled. 2. WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]). 3. tAS required if tCSP > 20ns. 51 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 41. Burst WRITE at End-of-Row (Wrap Off) VIH CLK VIL VIH tCLK A[20:0] VIL VIH ADV# VIL VIH UB#/LB# VIL VIH tHD Note 2 tCSP CE# VIL VIH OE# VIL VIH WE# VIL VIH tSP tHD Valid Intput DQ[15:0] VIL VOH Valid Intput End of row tKOH tKHTL tHZ tHZ High-Z WAIT VOL Don't Care Note: 1. Non-default BCR settings for burst WRITE at end of row: fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as solid line) 2. For burst WRITEs, CE# must go HIGH before the second CLK after the WAIT period begins(befor the second CLK after WAIT asserts with BCR[8]=0, or before the third CLK after WAIT asserts with BCR[8]=1). 52 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 42. Burst WRITE Row boundary crossing CLK VIH VIL VIH tCLK A[20:0] VIL VIH ADV# VIL VIH UB#/LB# CE# OE# VIL VIH VIL VIH VIL WE# VIH VIL VIH tSP tHD Valid input End of row Valid input Valid output Valid output DQ[15:0] WAIT VIL VOH VOL Valid input tKTHL tKOH Note 2 tKTHL tKOH Don't Care Note: 1. Non-default BCR settings for burst WRITE at end of row : Fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as solid line) 2. WAIT will be assert for LC or LC + 1 cycles for variables latency, or LC cycles for fixed latency. 53 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 43. Burst WRITE Followed by Burst READ tCLK CLK VIH VIL tSP tHD Valid Address tSP tHD Valid Address A[20:0] VIH VIL ADV# VIH VIL tSP tHD tHD tCBPH tSP tHD tCSP CE# VIH VIL Note 2 tCSP tOHZ OE# VIH VIL tSP tHD tSP tHD WE# VIH VIL LB#/UB# WAIT DQ[15:0] IN/OUT VIH VIL VOH VOL VIH tSP tHD tBOE High-Z High-Z tSP tHD VOH tACLK D1 D2 D3 VOL tKOH Valid Output Valid Output Valid Output Valid Output High-Z VIL D0 High-Z Don't Care Undefined Note: 1. Non-default BCR settings for burst WRITE followed by burst READ: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. CE# can stay LOW between burst READ and burst WRITE operations, but CE# must not remain LOW longer than tCEM. See burst interrupt diagrams for cases where CE# stays LOW between bursts. 54 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 44. Burst READ Interrupted by Burst READ or WRITE READ Burst interrupted with new READ or WRITE. See Note 2. tCLK CLK VIH VIL tSP tHD Valid Address tSP tHD Valid Address A[20:0] VIH VIL ADV# VIH VIL tSP tHD tCSP tSP tHD CE# VIH VIL tCEM (Note 3) tSP tHD tHD tSP tHD WE# VIH VIL tKHTL High-Z WAIT OE# LB#/UB# VOH VOL VIH tBOE tCEW tOHZ tBOE tOHZ 2nd Cycle READ VIL VIH 2nd Cycle READ VIL tACLK Valid Output tKOH High-Z Valid Output Valid Output Valid Output Valid Output DQ[15:0] OUT VOH 2nd Cycle READ VOL tACLK OE# VIH 2nd Cycle Write VIL VIH LB#/UB# 2nd Cycle Write V IL tSP tHD High-Z DQ[15:0] IN VIH 2nd Cycle Write VIL D0 D1 D2 D3 Don't Care Undefined Note: 1. Non-default BCR settings for burst READ interrupted by burst READ or WRITE: Fixed or variable latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision. 2. Burst interrupt shown on first allowable clock (i.e., after the first data received by the controller). 3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM. 55 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 45. Burst WRITE Interrupted by Burst WRITE or READ - Variable Latency Mode tCLK WRITE Burst interrupted with new WRITE or READ. See Note 2. CLK VIH VIL tSP tHD Valid Address tSP tHD Valid Address A[20:0] VIH VIL ADV# VIH VIL tSP tHD tCSP tSP tHD CE# VIH VIL tCEM (Note 3) tSP tHD tHD tSP tHD WE# VIH VIL tKHTL High-Z High-Z WAIT VOH VOL tCEW OE# VIH 2nd Cycle WRITE VIL VIH VIL tSP tHD LB#/UB# 2nd Cycle WRITE tSP tHD High-Z tSP tHD D0 tBOE D1 D2 D3 tOHZ DQ[15:0] IN VIH 2nd Cycle WRITE VIL D0 VIH VIL VIH VIL VOH VOL VOH OE# 2nd Cycle READ tSP tHD LB#/UB# 2nd Cycle READ tACLK High-Z VOL Valid Output tKOH Valid Output Valid Output Valid Output DQ[15:0] OUT 2nd Cycle READ Don't Care Undefined Note: 1. Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in variable latency mode: Variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision. 2. Burst interrupt shown on first allowable clock (i.e., after first data word written). 3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM. 56 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 46. Burst WRITE Interrupted by Burst WRITE or READ - Fixed Latency Mode tCLK WRITE Burst interrupted with new WRITE or READ. See Note 2. CLK VIH VIL tSP tHD Valid Address tSP tHD Valid Address A[20:0] VIH VIL ADV# VIH VIL tSP tHD tCSP tAVH tSP tHD CE# VIH VIL tCEM (Note 3) tSP tHD tHD tSP tHD WE# VIH VIL tKHTL High-Z High-Z WAIT OE# 2nd Cycle WRITE VOH VOL VIH VIL VIH VIL VIH tCEW tSP tHD LB#/UB# 2nd Cycle WRITE tSP tHD High-Z tSP tHD D0 tBOE D1 D2 D3 tOHZ DQ[15:0] IN 2nd Cycle WRITE VIL D0 VIH VIL VIH VIL VOH VOL VOH OE# 2nd Cycle READ tSP tHD LB#/UB# 2nd Cycle READ tACLK High-Z VOL Valid Output tKOH Valid Output Valid Output Valid Output DQ[15:0] OUT 2nd Cycle READ Don't Care Undefined Note: 1. Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in fixed latency mode: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. Burst interrupt shown on first allowable clock (i.e., after first data word written). 3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM. 57 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 47. Asynchronous WRITE Followed by Burst READ tCLK CLK A[20:0] VIH VIL VIH Valid Address VIL Valid Address Valid Address tWC tWC tSP tHD tAVS tVP tVPH tCVS tCW tAVH tAW tWR ADV# VIH VIL VIH tSP tHD tVS tCBPH Note 2 tCSP CE# VIL VIH VIL VIH tAS tOHZ OE# tAS tWP tWC tWPH tBW tSP tHD WE# VIL VIH VIL VOH tSP tBOE tHD LB#/UB# tCEW tDH High-Z WAIT DQ[15:0] IN/OUT High-Z VOL VIH tDW VOH tACLK High-Z VOL Valid Output tKOH Valid Output Valid Output Valid Output Data Data VIL Don't Care Undefined Note: 1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning to fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. 58 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 48. Asynchronous WRITE (ADV# LOW) Followed By Burst READ tCLK CLK A[20:0] VIH VIL VIH Valid Address VIL Valid Address Valid Address tWC tWC tSP tHD tAW tWR ADV# VIH VIL VIH tSP tCBPH tCSP tHD tCW CE# VIL VIH VIL VIH VIL VIH Note 2 tOHZ OE# tWP tWC tWPH tBW tSP tHD WE# tSP tCEW tBOE tHD LB#/UB# VIL VOH WAIT DQ[15:0] IN/OUT VOL VIH VIL High-Z tDH High-Z tDW Data VOH VOL tACLK High-Z tKOH Valid Output Valid Output Valid Output Valid Output Data Don't Care Undefined Note: 1. Non-default BCR settings for asynchronous WRITE, with ADV# LOW, followed by burst READ: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning to fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. 59 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 49. Burst READ Followed by Asynchronous WRITE (WE#-Controlled) tCLK CLK VIH VIL tSP tHD A[20:0] VIH Valid Address VIL tWC Valid Address ADV# VIH VIL tSP tHD tHD tHZ tBOE tOHZ tCBPH Note 2 tAW tWR CE# VIH VIL tCSP tCW OE# VIH VIL tSP tHD tOLZ tAS tWP tWPH WE# VIH VIL LB#/UB# VIH VIL VOH VOL VOH tSP tKHTL tBW tCEW High-Z tCEW High-Z tHZ WAIT tACLK High-Z tKOH tDW tDH DQ[15:0] Valid Output Valid Input VOL READ Burst Identified (WE# = HIGH) Don't Care Undefined Note: 1. Non-default BCR settings for burst READ followed by asynchronous WE#-controlled WRITE: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs; asynchronous operation begins at the falling edge of ADV#. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. 60 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 50. Burst READ Followed by Asynchronous WRITE Using ADV# tCLK CLK VIH VIL VIH Valid Address VIL Valid Address tSP tHD A[20:0] tAVS tSP tHD tVP tAVH tVS ADV# VIH VIL tAW tCSP tHD tHZ tBOE tSP tHD tOLZ tOHZ tCBPH Note 2 tAS CE# VIH VIL VIH VIL tCW OE# tAS tWP tWPH WE# VIH VIL VIH VIL tSP tHD tBW LB#/UB# WAIT VOH VOL tCEW High-Z tKHTL High-Z tCEW tHZ DQ[15:0] VOH VOL tACLK High-Z tKOH tDW Valid Input tDH Valid Output READ Burst Identified (WE# = HIGH) Don't Care Undefined Note: 1. Non-default BCR settings for burst READ followed by asynchronous WRITE using ADV#: Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. 2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning from fixed-latency burst READs; asynchronous operation begins at the falling edge of ADV#. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. 61 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 51. Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW A[20:0] VIH Valid Address VIL Valid Address Valid Address tAW tWR tAA ADV# VIH VIL CE# VIH VIL tCW tCPH Note 1 tLZ tHZ OE# VIH VIL tOE tAS tWP tWC tWPH tBW tHZ tBLZ tOHZ WE# VIH VIL tBHZ LB#/UB# WAIT DQ[15:0] IN/OUT VIH VIL VOH VOL VIH VIL tHZ tDH High-Z Data tDW VOH Data tOLZ High-Z VOL Valid Output Don't Care Undefined Note: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh interval. Otherwise, tCPH is only required after CE#-controlled WRITEs. 62 Preliminary EMC326SP16AJ 2Mx16 CellularRAM Figure 52. Asynchronous WRITE Followed by Asynchronous READ A[20:0] VIH Valid Address VIL VIH Valid Address Valid Address tAVS tAVH tAW tWR tAA ADV# VIL VIH VIL tVP tVS tCPH tLZ tHZ CE# tCW tAS Note 1 OE# VIH VIL VIH tOE tOLZ tOHZ tAS tWP tWC tWPH WE# VIL VIH VIL VOH tCVS tBW tBLZ tBHZ LB#/UB# WAIT DQ[15:0] IN/OUT VOL VIH tDH High-Z tDW VOH Data Data VOL VIL High-Z Valid Output Don't Care Undefined Note: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh interval. Otherwise, tCPH is only required after CE#-controlled WRITEs. 63 Preliminary EMC326SP16AJ 2Mx16 CellularRAM MEMORY FUNCTION GUIDE EM X XX X X X XX X X X - XX XX 1. EMLSI Memory 2. Device Type 3. Density 4. Function 5. Technology 6. Operating Voltage 1. Memory Component 2. Device Type 6 ---------------------- Low Power SRAM 7 ---------------------- STRAM C ---------------------- CellularRAM 3. Density 4 ----------------------- 4M 8 ----------------------- 8M 16 --------------------- 16M 32 --------------------- 32M 64 --------------------- 64M 28 --------------------- 128M 4. Function 2 ----Multiplexed async. 3-----Demultiplexed async. with page mode 4-----Demultiplexed async. with direct DPD 5-----Multiplexed sync. 6-----Optional mux/demuxed sync. 5. Technology S ----------------------- Single Transistor & Trench Cell 6. Operating Voltage V ----------------------- 3.3V U ----------------------- 3.0V S ----------------------- 2.5V R ----------------------- 2.0V P ----------------------- 1.8V L ----------------------- 1.5V 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 12. Power 11. Speed 10. PKG 9. Option 8. Version 7. Organization 8. Version Blank ----------------- Mother die A ----------------------- 2'nd generation B ----------------------- 3'rd generation C ----------------------- 4'th generation D ----------------------- 5'th generation 9. Option Blank ---- No optional mode H ----------- Demultiplexed with DPD J ------------ Demultiplexed with DPD & RBC K ------------ Multiplexed with RBC L ------------ Multiplexed with DPD & RBC 10. Package Blank ---------------------- Wafer S ---------------------- 32 sTSOP1 T ---------------------- 32 TSOP1 U ---------------------- 44 TSOP2 P ---------------------- 48 FPBGA Z ---------------------- 52 FPBGA Y ---------------------- 54 FPBGA V ---------------------- 90 FPBGA 11. Speed (@async.) 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 90 ---------------------- 90ns 10 --------------------- 100ns 12 --------------------- 120ns 12. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power (Pb-Free&Green) L ---------------------- Low Power 64 |
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